module apb_to_core
#(
  parameter CORE_BUS_WIDTH = 32,
  parameter CORE_ADDR      = 4
)(
  //OUTPUTS
  output [CORE_BUS_WIDTH - 1:0] PRDATA,         //APB Read Bus
  output PREADY,                                //APB Ready Signal
  output PSLVERR,                               //APB Error Signal
  output [CORE_BUS_WIDTH - 1:0] core_bus_wr,    //Core Write bus
  output core_write_en,                         //Core write enable
  output core_read_en,                          //Core read enable
  output [CORE_ADDR - 1:0] core_addr,           //Core address bus
  //INPUTS
  input [CORE_BUS_WIDTH - 1:0] PWDATA,          //APB Write Bus
  input [CORE_ADDR - 1:0] PADDR,                //APB Address Bus
  input PSEL,                                   //APB Select Signal
  input PENABLE,                                //APB Enable Signal
  input PWRITE,                                 //APB Read/Write Signal
  input PCLK,                                   //APB Clock
  input PRESETn,                                //APB Reset
  input [CORE_BUS_WIDTH - 1:0] core_bus_rd,     //Core Read Bus
  input core_busy_n                             //Indicates that core is busy
);

  localparam CONFIG_REG = 4'b1000;
  
  assign core_bus_wr   = PWDATA;
  assign PRDATA        = core_bus_rd;
  assign core_addr     = PADDR;//(PSEL) ? PADDR : 4'b1000;//melhorar isso
  assign core_write_en = (PSEL && PWRITE && PENABLE);
  assign core_read_en  = (PSEL && !PWRITE);
  assign PSLVERR       = (core_write_en || (core_read_en && core_addr != CONFIG_REG)) && !core_busy_n;//isso tb
  assign PREADY        =  1'b1;
   
endmodule
